TBD.

RISC-V is an open-source instruction set architecture (ISA) for computer processors. It is designed to be simple, modular, and extensible, with a minimalist approach to instruction set design that aims to provide flexibility, performance, and energy efficiency. The class provides an introduction to RISC-V and vector supercomputing. A particular focus will be given to the RISC-V vector extensions (RVV) and especially to an implementation using large vectors. Students will learn how RVV compares to other vector architectures and explore a design point leveraging up to 16-kb-wide vectors. Students will be exposed to methodology, tools and libraries available for vectorization and the challenges and limitations coming with them. A prototype platform implementing a European RISC-V CPU supporting the RVV extension will be presented for testing and analyzing simple codes and parallel scientific applications.

The tutorial will consist of a mix of practical hands-ons on the Monte Cimone RISC-V Cluster accompanied by short explanations. This tutorial will guide the student in applying concepts from computing architecture to evaluate the performance of the underlying HW and measure its bottleneck. To this purpose performance monitoring tools will be used as well as practical case studies will be discussed.

TBD

This talk presents some guidelines for writing an HPC research paper. We will start discussing how to organize and present research ideas.

We then analyze good and bad practices in benchmarking and results presentation with practical and interactive examples. We discuss some common mistakes that might impact the results' meaningfulness and interpretability. Last, we conclude by discussing how to guarantee the reproducibility of research results.

In this short lecture will be presented an overview of the general state of art of the world of High Performance Computing, focusing on the present technologies and with a glimpse of the future. 

CINECA, national consortium aimed at providing HPC resources for academical and industrial research, will discuss the infrastructure that can be made available to their users, with a major focus on Leonardo, the pre-exascale cluster ranked among the first ten most performant supercomputers in the World.

Programming modern high-performance computing systems is challenging due to the need to efficiently program GPUs and accelerators, handle data movement between nodes, and support optimization for modern workloads such as neural networks. The C++ language has been greatly enhanced in recent years with features that greatly increase productivity. In particular, the C++-based SYCL standard provides a powerful programming model for heterogeneous systems that can target a wide range of devices, including multicore CPUs, GPUs, FPGAs, and accelerators.

The course consists of two sessions. In the first session, attendants will learn about the architecture of modern GPUs, including the execution model, the memory model, and other key concepts. Attendants will be able to write GPU kernels in SYCL using parallel_for semantics and different memory access models. They will also understand the similarities and differences between different vendors including AMD, Intel, and NVIDIA, and implement basic optimization techniques.

The second session will focus on advanced SYCL topics, including group algorithms, kernel reduction, atomics, and specialization constants. The session will also present ongoing research efforts to design advanced SYCL-based high-level programming semantics that provide advanced optimizations. In particular, we will see SYCL extensions dealing with cluster of accelerators and workload distribution (CELERITY), energy efficient computing (SYnergy), support for approximate computation (SYprox), and support for tensor units (joint_matrix).

This talk introduces the basics of two essential aspects of HPC: distributed memory programming and interconnection networks.

We will analyze the challenges in writing scalable distributed memory applications and the impact the underlying interconnection network might have on application performance. We will cover the message-passing model, collective communication algorithms and how they are optimized for the underlying network, in-network computing, and the impact of congestion control and routing on performance variability.

The OpenACC programming model provides a directive-based approach to accelerate parallel computing on heterogeneous architectures, such as GPUs and multi-core CPUs. Developers annotate their code with compiler directives, guiding the parallelization and optimization process. OpenACC tries as a bridge between productivity and performance in the era of heterogeneous computing. This short tutorial will cover the fundamentals of Accelerated Computing with OpenACC, including exercises in C/C++ and Fortran.

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The OpenACC programming model provides a directive-based approach to accelerate parallel computing on heterogeneous architectures, such as GPUs and multi-core CPUs. Developers annotate their code with compiler directives, guiding the parallelization and optimization process. OpenACC tries as a bridge between productivity and performance in the era of heterogeneous computing. This short tutorial will cover the fundamentals of Accelerated Computing with OpenACC, including exercises in C/C++ and Fortran.

AI Data-center HW architecture
Artificial Intelligence, and specifically deep neural networks become the single most interesting application. It is expected that a growing percentage of the world’s compute power will be dedicated to training and inferencing of neural networks for many tasks. Training large neural network models such as Large Language Models (LLM) require specialized systems and standard datacenters cannot train such models in an efficient way. In this talk we will focus on the connectivity requirements for large scale datacenters (AI factories) with the focus on LLM workloads connecting tens of thousands of processing engines (GPUs). We will discuss requirements and how in-network computing can accelerate today's and tomorrow's AI workloads.

An Introduction to NVIDIA BlueField 3 DPUs
As we scale systems, the performance of communications becomes increasingly critical, necessitating the optimization of these processes. A promising approach to optimization involves delineating specific parts of the communication stack for offloading to the network, thereby enhancing efficiency and conserving CPU cycles. Unlike traditional hardware offloads, Data Processing Units (DPUs) feature programmable engines. These allow both applications and communication libraries to define and delegate tasks for execution directly on the network card, offering a new network programming paradigm. In this talk, we will delve into the programmable components of the NVIDIA BlueField 3 DPU. We'll explore its architecture, the programming models, and potential use cases, providing insights into how these technologies can be leveraged to optimize large-scale communication systems.

In recent times, GPUs have taken the lead as primary accelerators in high-performance systems, concentrating much computational power in GPU clusters. While multi-GPU acceleration benefits many HPC and ML applications, inter-GPU communication, handled traditionally by the host, can hinder scalability. The host traditionally controls execution by managing kernels, communication, and synchronization. This CPU involvement can be fully shifted to devices, improving performance for multi-GPU applications. 

In this talk, first I present a fully autonomous multi-GPU execution model, eliminating CPU involvement after the initial kernel launch. Our CPU-free model leverages techniques like persistent kernels and device-initiated communication, reducing communication overhead. We validate the model on iterative solvers—2D/3D Jacobian stencil and Conjugate Gradient (CG). Second, I introduce a multi-GPU communication profiling tool founded on NVBit and relying on instrumentation. Our tool excels in tracking both peer-to-peer data transfers and communication library calls. The tool provides a variety of visualization modes and levels of detail, ranging from a broad overview of data movement across the system to the precise instructions and memory addresses involved. 

Linear Algebra (LA) libraries are key components in any software platform for scientific and

engineering computing. Solution of large linear systems and/or the computation of a few

eigenvalues/eigenvectors of an operator are indeed at the core of physics-driven numerical

simulations relying on partial differential equations and often represents a main bottleneck in data-

driven procedures, such as model reduction, graph analysis and scientific machine learning.

In this lecture I will give an introduction to scientific libraries for dense LA, such as BLAS, Linpack

and its successors, which represent “de facto” standard platforms for scientific code development

and also benchmarks for new proposals of hardware/software architectures for HPC. Then I will

focus on fundamental algorithms for sparse LA and present some recent research efforts to propose

new algorithms and software libraries for high-end GPU-accelerated hybrid architectures.

Progress in science is deeply bound to the effective use of high-performance computing infrastructures and to the efficient extraction of knowledge from vast amounts of data. Such data comes from different sources that follow a cycle composed of pre-processing steps for data curation and preparation for subsequent computing steps, and later analysis and analytics steps applied to the results. However, scientific workflows are currently fragmented in multiple components, with different processes for computing and data management, and with gaps in the viewpoints of the user profiles involved. Our vision is that future workflow environments and tools for the development of scientific workflows should follow a holistic approach, where both data and computing are integrated in a single flow built on simple, high-level interfaces. In this presentation, we present our vision for novel definition of workflows that integrate the different data and compute processes, dynamic runtimes to support the execution of the workflows in complex and heterogeneous computing infrastructures efficiently, both in terms of performance and energy. These infrastructures are spawn across the so-called computing continuum, that includes highly distributed resources, from sensors and instruments, and devices in the edge, to High-Performance Computing and Cloud computing resources.